1. Field of the Invention
This invention relates to a circuit generating a voltage signal which is independent of temperature and has low sensitivity to variations in process parameters.
More particularly, the invention relates to a circuit comprising at least an output MOS transistor, through which an output current flows, being connected to a first voltage reference, and having a gate terminal connected to a bias network connected between a second voltage reference and said first voltage reference.
2. Description of the Related Art
In order to generate a signal which is independent of temperature and has low sensitivity to process parameter variations, temperature-independent current generators have been used, which charge and discharge a capacitor.
In order to provide such a current generator, the current-voltage characteristic ID(Vgs) of a MOS transistor is used. As schematically illustrated in FIG. 1, a reference voltage Vgsx can always be found at which the current IDX flowing through a MOS transistor will not vary with temperature T.
In particular, FIG. 1 illustrates the current-voltage characteristic of a MOS transistor at three different temperatures T1, T2 and T3. This characteristic shows a zero-temperature-coefficient point X at the reference voltage Vgsx where the current ID does not vary with temperature.
Thus, by applying such a bias voltage Vgsx between the gate and source terminals of a MOS transistor, the transistor is led to conduct a temperature-independent current IDX between the source and drain terminals.
In particular, the current ID, or drain current, which flows through a MOS transistor operating in its linear region, is given by:                               I          D                =                                            1              2                        ·            μ            ·            Cox            ·                          W              L                        ·                                          (                                  Vgs                  -                  Vth                                )                            2                                =                                                    1                2                            ·              μ              ·              Cox              ·                              W                L                            ·              Δ                        ⁢                          xe2x80x83                        ⁢                          V              2                                                          (        1        )            
where: xcexc is electron mobility; Cox is the capacitance of silicon oxide; Vgs is the bias voltage of the gate terminal, that is, the voltage applied between the gate and source terminals; and Vth is the transistor threshold voltage.
Those parameters which vary appreciably with the temperature T are the mobility xcexc and the threshold voltage Vth, while the variation of the capacitance Cox is negligible.
In particular, the threshold voltage Vth is known to decrease almost linearly as the temperature T increases, this variation obeying the following equation:
Vth(T)=Vth(T0)+CTMOSxc2x7(T-T0)xe2x80x83xe2x80x83(2)
where CTMOS is the thermal coefficient of the MOS transistor and T0 is room temperature.
Thus, the term depending on the voltage variation, xcex94V2, increases in equation (1) as the square of the change in temperature T.
Also, the mobility xcexc, as a function of the temperature T, obeys the following equation:                               μ          ⁢                      xe2x80x83                    ⁢                      (            T            )                          =                              μ            0                    ·                                    (                              T                                  T                  0                                            )                                      -              α                                                          (        3        )            
where xcex1 is a coefficient with a value in the range of 1.5 to 2.
The zero-temperature-coefficient point X in the diagram of FIG. 1, where the current ID and the voltage Vgs are independent of the temperature T, is analytically calculated by assuming that the first derivatives of those functions which represent the values of ID and Vgs with respect to the temperature T are simultaneously zero.
If ∂ID(T)/∂T=0, then:                               Vgs          ⁡                      (            t            )                          =                              2            ·                          T              α                        ·                          (                                                                    ∂                                          Vgs                      ⁡                                              (                        T                        )                                                                                                  ∂                    T                                                  -                                  CT                  MOS                                            )                                +                      Vth            ⁡                          (                              T                0                            )                                +                                    CT              MOS                        ·                          (                              T                -                                  T                  0                                            )                                                          (        4        )            
Now, if ∂Vgs(T)/∂T=0, then:
xcex1=2
In conclusion, there exists a point where, once an appropriate voltage Vgs is set, the current ID flowing through a MOS transistor does not vary with temperature if the coefficient xcex1 equals 2.
However, the variation of the current ID with the temperature T is quite small when the coefficient xcex1 is between 1.5 and 2.
As for the variations related to the manufacturing process of the MOS transistor, it is well known that the threshold voltage Vth and the capacitance Cox are appreciably affected by such variations, causing the current ID to also become dependent on process variations.
On the other hand, the mobility xcexc varies very little with the variations in process parameters; it primarily depends on the dopant element, and can be set with an accuracy of within 5%, so that the mobility xcexc is one of the best controlled parameters.
Thus, it is necessary to compensate the error introduced by the capacitance Cox variation, or the variation in the thickness of the gate oxide, and by the threshold voltage Vth variation.
If the capacitor C1 dielectric is formed using the gate oxide layer of the MOS transistor, variations in the capacitance Cox are compensated by the capacitor C1, thus reducing its dependence on the process parameter variations.
As for the threshold voltage Vth of the MOS transistor, a circuit configuration, connected to the capacitor C1 and the MOS transistor functioning as a current generator, is used in order to force the transistor to operate at the calculated zero-temperature-coefficient point X to decrease its dependence on temperature.
A known circuit that generates a constant voltage signal is generally shown at 1 in FIG. 2, in schematic form.
The circuit 1 comprises a capacitor C1 connected between a first supply voltage reference Vcc and a constant current generator 2, the circuit 1 basically consisting of a MOS transistor Mout and a bias network 3.
The transistor Mout has a gate terminal G connected to the bias network 3, a drain terminal D connected to a terminal of the capacitor C1 to form an output terminal OUT, and a source terminal S connected to a second voltage reference, specifically a ground reference GND.
The voltage Vout at the node OUT, therefore, depends on the charged state of the capacitor C1.
The bias network 3 comprises first M1 and second M2 MOS transistors connected in a diode configuration, that is, each with its respective gate and drain terminals connected, these transistors being connected in series between the supply voltage Vcc and ground GND references. In particular, the first transistor M1 is connected to the supply voltage reference Vcc through a current mirror 4.
The current mirror 4 is further connected to the ground reference GND through a series of a first bipolar transistor Q1 and a first resistive element R1, the latter comprising a resistor pair R1a and R1b. 
The second transistor M2 is further connected to the ground reference GND through a second resistive element R2, the latter comprising a resistor pair R2a and R2b. 
The bias network 3 also includes a third MOS transistor M3, connected between the supply voltage reference Vcc and the gate terminal G of the transistor Mout, the latter connected to the ground reference GND through a second bipolar transistor Q2 and a third resistive element R3 connected in series.
The third transistor M3 has a gate terminal connected to the gate terminal of the first transistor M1.
Finally, the first Q1 and second Q2 bipolar transistors have base terminals in common and connected to a bias voltage reference Vpol.
As shown in FIG. 2, the current mirror 4 particularly comprises fourth Q4, fifth Q5 and sixth Q6 bipolar transistors which are connected to the supply voltage reference Vcc through fourth R4, fifth R5 and sixth R6 resistive elements, respectively.
The fourth bipolar transistor Q4 is further connected to the first bipolar transistor Q1, and has a base terminal connected to the base terminal of the fifth bipolar transistor Q5, the latter in turn connected to the first MOS transistor M1.
The sixth bipolar transistor Q6 is connected to the ground reference GND, and has a base terminal connected to the first bipolar transistor Q1.
The operation of the circuit 1 shown in FIG. 2 will now be discussed.
The bias network 3 essentially functions to bias the MOS transistor MOUT at the point where, with a given voltage Vgs set, the current ID flowing through it does not vary with the temperature T.
In particular, the voltage Vgsout between the gate and source terminals of the transistor MOUT is given by:
Vgsout(T)=Vgs1+Vgs2+xcex94V(T)xe2x88x92Vgs3xe2x80x83xe2x80x83(5)
where: Vgs1, Vgs2 and Vgs3 are the gate-source voltages of the transistors M1, M2 and M3; and xcex94V(T) is an appropriate voltage added by the bias network 3 in order to stabilize Vgsout with respect to temperature.
Equation (5) may also be written as:                               Vgsout          ⁡                      (            T            )                          =                              Vth            ⁡                          (              T              )                                +                                                    2                ·                I                ·                L1                                            μ                ·                Cox                ·                W1                                              +                                                    2                ·                I                ·                L2                                            μ                ·                Cox                ·                W2                                              +                      Δ            ⁢                          xe2x80x83                        ⁢                          V              ⁡                              (                T                )                                              -                                                                      2                  ·                  2                                ⁢                                  I                  ·                  L3                                                            μ                ·                Cox                ·                W3                                                                        (        6        )            
where: L1/W1, L2/W2 and L3/W3 are the aspect ratios of the transistors M1, M2 and M3; I is the current flowing through the transistors M1 and M2; and 21 is the current flowing through the transistor M3.
The overall contribution of the expressions under the radical signs can be eliminated if transistors with suitably selected sizes are used. Specifically in this case, given:
xe2x80x83(W1/L1)=(W2/L2)=2(W3/L3),
the following equation is arrived at:
Vgsout(T)=xcex94V(T)+Vth(T)=xcex94V(T)+Vth(T0)+CTMOS( T-T0)xe2x80x83xe2x80x83(7)
The desired zero-temperature-coefficient point X, that is, the point where the current ID and the voltage Vgs of the transistor MOUT are constant when the temperature T varies, is found by substituting ∂Vgsout(t)/∂T=0 in equation (4) when applied to the transistor MOUT, so that:                               Vgsout          ⁡                      (            T            )                          =                                            -                              2                α                                      ·            T            ·                          CT              MOS                                +                      Vth            ⁡                          (                              T                0                            )                                +                                    CT              MOS                        ⁡                          (                              T                -                                  T                  0                                            )                                                          (        8        )            
From equation (8), at room temperature To:                               Vgsout          ⁡                      (                          T              0                        )                          =                                            -                              2                α                                      ·                          T              0                        ·                          CT              MOS                                +                      Vth            ⁡                          (                              T                0                            )                                                          (        9        )            
A comparison of equations (9) and (7) shows that, again at room temperature T0:                               Δ          ⁢                      xe2x80x83                    ⁢                      V            ⁡                          (                              T                0                            )                                      =                              -                          2              α                                ·                      T            0                    ·                      CT            MOS                                              (        10        )            
Assuming the derivative of the voltage Vgsout with respect to temperature to be zero, then equation (7) becomes:                                                         ∂              Δ                        ⁢                          xe2x80x83                        ⁢            V            ⁢                          xe2x80x83                        ⁢                          (              T              )                                            ∂            T                          =                  -                      CT            MOS                                              (        11        )            
In summary, for the transistor MOUT to work at the desired zero-temperature-coefficient point X and function independently of temperature, the following additional voltage difference xcex94V should be applied:                               Δ          ⁢                      xe2x80x83                    ⁢                      V            ⁡                          (              T              )                                      =                                            -                              2                α                                      ·                          T              0                        ·                          CT              MOS                                -                                    CT              MOS                        ⁡                          (                              T                -                                  T                  0                                            )                                                          (        12        )            
In particular, the bias network 3 of FIG. 2 provides a bias voltage to the transistor MOUT which obeys equation (12). In fact, the first bipolar transistor Q1, which has a similar thermal gradient to that of the transistor MOUT, has a voltage VBE which is substantially independent of process variations.
It should be noted that the same result could not be obtained by using a temperature-independent voltage reference circuit (as provided by a band-gap circuit, for example), and subtracting a gate-source voltage Vgs therefrom. This is because the voltage difference xcex94V thus obtained depends on the threshold voltage of the MOS transistor used, and hence is heavily dependent on process variations, the transistor MOUT being directly biased by the bias voltage Vpol.
In particular, according to FIG. 2, the voltages at the ends of the first resistive element R1 are equal to the voltages at the ends of the second resistive element R2, since these elements have the same resistance and are supplied current by the current mirror 4.
The voltage difference xcex94V obtained by the circuit of FIG. 2 is therefore given by:
xcex94V(T)=Vpolxe2x88x92VBEl(T)=Vpolxe2x88x92VBEl(T0)xe2x88x92CTBJT(Txe2x88x92T0)xe2x80x83xe2x80x83(13)
where CTBJT is the thermal coefficient of the bipolar transistors.
An appropriate value of the bias voltage Vpol obtained from equation (13) for application to the bias network 3, in order to have the transistor MOUT operating at the desired zero-temperature-coefficient point X, is:                     Vpol        =                                            Δ              ⁢                              xe2x80x83                            ⁢                              V                ⁡                                  (                  T                  )                                                      +                                          V                BE1                            ⁡                              (                T                )                                              =                                                    -                                  2                  α                                            ·                              T                0                            ·                              CT                MOS                                      +                                          V                BE1                            ⁡                              (                                  T                  0                                )                                                                        (        14        )            
However, this solution has a disadvantage in that it requires a sufficiently accurate bias voltage reference Vpol so that the transistor MOUT can function in such a way as to lessen the effects of temperature.
Such a value of the bias voltage reference Vpol depends on the voltage VBEl(T0) of the first bipolar transistor Q1, such a voltage being dependent on the process variations.
Finally, the variation of the bias voltage VBEl(T0) with temperature follows a different pattern than the variation of the gate-source voltage of a MOS transistor with temperature, since MOS transistors and bipolar ones have different thermal coefficients (CTMOS=xe2x88x922.2 mV/xc2x0 C.; CTBJT=xe2x88x921.85 mV/xc2x0 C.).
This invention comprises a circuit generating a voltage signal which is independent of temperature and has low sensitivity to process parameter variations, the circuit requiring no special bias reference and overcoming the limitations of the prior art.
The basic idea on which this invention stands is one of using a bias network for a MOS transistor comprising a current generator element which has a thermal gradient that approximates the thermal gradient of the MOS transistor.
In particular, the current generator element comprises at least a first current generator formed by bipolar transistors, and a second current generator formed by a voltage reference which is independent of temperature, such as a band-gap reference.